1. Field of the Invention
The present invention relates generally to an integrated circuit and method for interfacing two voltage domains using a transformer, and more particularly to an integrated circuit and method for maintaining the integrity of an input reference clock signal in the presence of a noisy chip environment.
2. Background of the Invention
Phase-locked loops (PLLs) are analog circuits that are employed extensively in on-chip clock generation and redistribution systems. PLLs use phase/frequency correction to generate chip clock waveforms that in some way mimic the characteristics of an input reference clock signal. Ideally, the edges of the PLL-generated clock waveform are distributed to be precisely periodic, i.e., the duration of successive clock cycles are constant. Deviation from this ideal behavior is measured using a figure-of-merit called “clock jitter”. Excessive clock jitter can be catastrophic and lead to system timing failures.
One of the leading contributors to clock jitter is electrical noise, which can manifest itself as a delay variation in the PLL feedback loop, transient power bus or substrate noise at the PLL itself, or variations in the edge displacement of the (input) reference clock signal.
As illustrated in FIG. 1, in at least one prior art circuit design 20, a reference clock signal (not shown) generated by an off-chip clock generator circuit 21 is passed through an I/O receiver circuit 22, located in a digital region 23 of chip 24. To protect the receiver circuit from electrostatic discharge, or ESD (i.e., static electricity), the receiver circuit input pad 25 is typically tied to an ESD protection circuit 26 that clamps the input voltage to a level below the gate breakdown voltage of the receiver circuit. In common implementations, the input receiver, pad, and ESD circuits share their environment, i.e., power grid wiring, coupled capacitance, etc., with on-chip “noisy” circuits in the digital chip region. This common environment often causes noise 27 to be coupled to the receiver input reference clock signal (not shown) that is passed to a PLL 28 in an analog region 30 of chip 24. As a result, electrical noise 27 in prior art designs may cause excessive clock jitter.